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 HCF4028B
BCD TO DECIMAL DECODER
s
s
s
s
s s
s
s s
BCD TO DECIMAL DECODING OR BINARY TO OCTAL DECODING HIGH DECODED OUTPUT DRIVE CAPABILITY "POSITIVE LOGIC" INPUTS AND OUTPUTS: DECODED OUTPUTS GO HIGH ON SELECTION MEDIUM SPEED OPERATION : tPHL, tPLH = 80ns (Typ.) at VDD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4028BEY HCF4028BM1 T&R HCF4028M013TR
DESCRIPTION HCF4028B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4028B is a BCD to DECIMAL or BINARY to OCTAL decoder consisting of buffering on all 4
inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the four inputs, A to D, results in a high level at the selected one of 10 decimal decoded outputs. Similarly, a 3-bit binary code applied to inputs A through C is decoded in octal code at output 0 to 7 if D = "0". High drive capability is provided at all outputs to enhance dc and dynamic performance in high fan-out applications.
PIN CONNECTION
September 2002
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HCF4028B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 10, 13, 12, 11 10, 13, 12 3, 14, 2, 15, 1, 6, 7, 4, 9, 5 3, 14, 2, 15, 1, 6, 7, 4 8 16 SYMBOL A, B, C, D A, B, C 0 to 9 0 to 7 VSS VDD NAME AND FUNCTION BCD Data Inputs 3-Bit Binary Inputs Buffered DECIMAL Decoded Outputs Buffered OCTAL Decoded Outputs Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
INPUTS D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H 0 H L L L L L L L L L L L L L L L 1 L H L L L L L L L L L L L L L L 2 L L H L L L L L L L L L L L L L 3 L L L H L L L L L L L L L L L L OUTPUTS 4 L L L L H L L L L L L L L L L L 5 L L L L L H L L L L L L L L L L 6 L L L L L L H L L L L L L L L L 7 L L L L L L L H L L L L L L L L 8 L L L L L L L L H L L L L L L L 9 L L L L L L L L L H L L L L L L
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HCF4028B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF4028B
DC SPECIFICATIONS
Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
mA
mA
II
any input any input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) tPHL tPLH Propagation Delay Time (Clock to "Out") tTHL tTLH Transition Time (Carry Out Line) 5 10 15 5 10 15 Min. Typ. 175 80 60 100 50 25 Max. 350 160 120 200 100 50 ns Value (*) Unit
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF4028B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
TYPICAL APPLICATION The circuit shown in fig. 1 converts any 4-bit code to a decimal or hexadecimal code. Fig. 2 shows a number of codes and the decimal or hexadecimal number in these codes, which must be applied to the input pins of HCF4028B to select a particular output. For example: in order to get a "high" on output 8 the input must be either an 8 expressed in
4-bit binary code excess-3code.
or
a
15
expressed
in
5/10
HCF4028B
FIGURE 1 : CODE CONVERSION CIRCUIT
FIGURE 2 : CODE CONVERSION CHART
INPUT CODES INPUTS HEXA DECIMAL OUTPUT NUMBER DECIMAL
EXCESS 3 GRAY
4 BIT BINARY
4 BIT GRAY
EXCESS 3
AIKEN
D
C
B
A
4221
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
L L L L L L L L H H H H H H H H 6/10
L L L L H H H H L L L L H H H H
L L H H L L H H L L H H L L H H
L H L H L H L H L H L H L H L H
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 3 2 7 6 4 5 15 14 12 13 8 9 11 10
0 1 2 3 4 5 6 7 8 9
0 3 4 1 2
0 1 2 3 4
0 1 2
3 4
9 5 6 8 7 5 6 7 8 9
5 6
7 8 9
H L L L L L L L L L L L L L L L
L H L L L L L L L L L L L L L L
L L H L L L L L L L L L L L L L
L L L H L L L L L L L L L L L L
L L L L H L L L L L L L L L L L
L L L L L H L L L L L L L L L L
L L L L L L H L L L L L L L L L
L L L L L L L H L L L L L L L L
L L L L L L L L H L L L L L L L
L L L L L L L L L H L L L L L L
L L L L L L L L L L H L L L L L
L L L L L L L L L L L H L L L L
L L L L L L L L L L L L H L L L
L L L L L L L L L L L L L H L L
L L L L L L L L L L L L L L H L
L L L L L L L L L L L L L L L H
HCF4028B
FIGURE 3 : 6 BIT BINARY TO 1 OF 64 ADDRESS DECODER
FIGURE 4 : NEON READOUT (NIXIE TUBE) DISPLAY APPLICATION
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HCF4028B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4028B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF4028B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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